lockout or disarm classes of interrupts and often
specific interrupts within a class. Lower levels of
interrupts (class II through IV) can be locked out
(disarmed) or enabled (armed) by machine instruction.
The terms prevent/allow are also used in place of
enable/disable with some computers. The lower
priority interrupts are locked out so that they do not
interfere with higher level computer operations
(executive state or class I interrupt processing) while
they are in progress.
There are usually several specific class I interrupts
that cannot be locked out by instruction. These
interrupts would normally include any of the following:
CPU instruction fault
IOC instruction fault interrupts
INTERRUPTS AND INTERRUPT CODES.
Interrupt signals, as a rule, cause the computer to
reference a freed address in memory and execute the
subroutine (a series of instructions) identified by the
contents of the address.
The interrupt signal only
identifies the class of interrupt. Multiple interrupt types
within a class are usually defined by an accompanying
interrupt code or interrupt code word.
In older and smaller computers, the interrupt code
parallels the interrupt signal. In other words both the
interrupt signal (class I, II, or III) and identifying code
are received and processed by the CPU at the same time.
Since the interrupt processor tends to lockout interrupts
of the same class, this process tends to hold up or even
lose interrupts of the same or lower priority classes that
occur while the first interrupt is being processed.
Newer computers retain multiple interrupt codes of
the same class in an interrupt stack or interrupt
queue, usually contained in the I/O section. There
usually is a stack or queue for each interrupt class (I, II,
or III). Interrupt queues store their codes in first-in,
first-out (FIFO) order.
The interrupt signal would indicate to the CPU the
presence of at least one interrupt of the particular class.
The stack and queue arrangements allow the CPU to
sample the interrupt codes at its convenience. As each
code is processed, it is removed from the stack or queue
until the stack or queue is empty. The interrupt signal
would only drop if the stack or queue becomes empty.
New interrupt codes would simply be added to the stack
or queue as they occur. An empty stack or queue would
generate an interrupt signal when the first new code is
added to the stack or queue by the I/O circuits.
INTERRUPT HANDLING PROCESS. CPUs
follow a specific sequence of events when processing
an interrupt. Remember interrupt processing has
priority over normal program execution. We discuss
the general interrupt handling process in order of its
sequence. Figure 5-9 illustrates the general sequence
Figure 5-9.General sequence of an interrupt response.