computer uses even or odd parity. The process relies on the exclusive-OR operation to count the ones. Parity checks are designed to identiffy the loss (1 to 0) or gain (0 to 1) of a single bit during the read/write process. When the data is read from memory, it is checked for an even number of bits for even parity computers or an odd  number  of  bits  for  odd  parity  computers.  A difference causes the generation of a  parity error signal  or other type of error to the requestor. If no error condition exists, the parity bit is dropped and the computer continues processing. Parity checks do not provide for correction of the error condition. ERROR   BIT   DETECTION   AND/OR CORRECTION. —Newer computer designs use error detection   and   correction   circuitry   for   their semiconductor memories, modules, or pcb’s. The error detection  and  correction  circuits  allow  for  the  detection and correction of single bit errors and the detection of double and sometimes 3-bit errors during read/write operations. The error detection and correction circuits use a Hamming code to identify the configuration of ones and  zeros  stored  in  a  particular  memory  location  or group  of  bits. Additional storage for check bits is required for each memory address. The number of check bits varies with the number of data bits being tested. For instance, six check bits are used for a 16-bit data word. The check bits are generated by the error detection  and  correction  circuits  during  the  write operation  and  are  written  into  the  memory  address  with the data. During read operations, the stored check bits are compared  with  the  error  detection  and  correction generated check bits of the data read. Differences in the check bit patterns can be used to correct single bit data errors and at least identify the presence of double bit or greater  errors. The error detection and correction circuitry will indicate the detection of any error to the CPU.  In  computers  with  the  error  detection  and correction  capability,  the  correction  circuits  can  be enabled or disabled by CPU instruction. The error detection circuits, however, function at all times. Memory Protection Many computers provide controlled access to specified segments of memory through the use of memory protection registers. The memory protection register set  (usually three registers) is used to restrict read/write operations in the protected area. In one form of  the  memory  protection  register  set,  the  boundaries  of the protected area are defined by the  memory  protect lower  limit  register,  which  contains  the  lower boundary address and the  memory  protect  upper  limit register, which contains the upper boundary address. All addresses between the upper and lower limits are protected. The memory protection control register contains three control bits that determine the allowable operations   in   the   protected   area.   The   memory protection control bits are set (1) to allow each of the following three operations (in any combination): Read  instruction  (execute  protected) Read  operand  (read  protected) Write operand (write protected) After a request has been accepted, the memory protection logic checks the address to determine if it is in the protected area. If the address is within the boundaries,  the  operation  being  requested  is  checked  to see  if  it  is  allowable.  An  allowable  operation  is executed. In the event an attempted operation is not allowed, a  memory protect fault interrupt  is sent to the  requestor. Other forms of memory protection registers identify the following: Starting address Block size (number of addresses) Protection  function The basic protection functions are the same for all computers;  however,  some  computers  may  have  an additional control bit to allow indirect addressing within the protected area. Another   form   of   memory   protection   called memory lockout  is used by larger computers to prevent access to particular areas of memory by task state instructions. Memory lockout prevents task state programs  (application  programs)  from  accessing segments  of  main  memory  reserved  for  interrupt processing and other executive functions. The lockout feature is disabled when the CPU enters a particular executive or interrupt state and enabled when the CPU enters the task state. MEMORY TYPES As stated at the beginning of this topic, we have divided  the  memory  types  into  two  categories: read/write and read-only memories. You will learn more about these in the next two topics. 6-8