executing other instructions. Instructions or instruction
bytes are added to the rear of the queue until the queue
is full. When the execution unit has completed an
instruction, it simply takes the next instruction or
several instruction bytes from the front of the queue.
Instruction Operation Levels
The CPU executes instructions at two levels or
states: the executive state and the task state. Data bits
in the status indicating registers(s) are used to select the
desired active state.
Executive state Executive state, also called inter-
rupt state, instructions are designed to process what are
known as executive functions (primarily I/O and inter-
rupt processing) for multiprogramming operations. These
functions are included in the operating system programs.
There may be as many as four separate executive states
in newer computers, one for each class of interrupts.
Task state Task state instructions execute what
are called application functions. These functions
actually perform the work, such as solving the fire
control problem in a CDS/NTDS platform or
computing a sonobuoy pattern on a TSC platform.
The majority of machine instructions can be
executed in either the task or executive states. There
are a limited number of instructions that can be executed
only in the executive states. An example is privileged
instructions that are part of interrupts, which you will
learn more about later in this topic.
Those computers that have task and executive states
have at least one set of addressable registers for each
state. These addressable register types (accumulators,
index registers, base registers, and the like) are only
accessible by machine instruction when the computer
is in the applicable state. The register sets are enabled
and disabled automatically as the computer changes
states. In computers with four executive states, there
are five sets of addressable registers, one for the task
state and one for each executive state.
INSTRUCTION OPERAND ADDRESSING
Addressing is the process of locating the operand
(specific information) for a given operation. It is
similar to the process of obtaining your address so that
information can be sent to you. Once the computer
knows where to obtain the location of the operand, the
instruction can be carried out. If for instance, the
operand is in memory, the addressing technique
determines how to obtain the memory address of the
operand and how to use this address to locate the
operand and fetch it. If the operand is in one of the
CPUs registers, addressing is the means by which the
instruction specifies the selected register and the
operand is fetched. Because the length of instructions
and the number of bits per memory cell vary between
types of instructions and computers, there is a variety
of ways the operand maybe obtained.
Up to this point we have covered timing and instruc-
tion control and execution. The following information
is designed to the together the overall operation of the
computer through the study of interrupts and interrupt
processing. We first cover the definition of an interrupt
and the types and classifications of interrupts you will
encounter in computer systems. Then, we cover how
computers handle interrupts and what happens within
the computer hardware and software.
An interrupt is defined as a break in the normal flow
of operation of a computer caused by an interrupt
signal. The break occurs in such a way that the
operation can be resumed from the point of the break at
a later time with exactly the same conditions prevailing.
Interrupts are a method of diverting the attention of
the computer from whatever process or program it is
performing to the special condition or event that caused
the interrupt signal. Interrupts allow the computer to
respond to high priority demands and still be able to
perform normal or lower priority processing. When the
condition that caused the interrupt signal to occur has
been addressed or processed, the computers attention
can be returned to the process or program it was
executing before the interrupt with the exact same
Interrupts can occur either
asynchronously or synchronously within the CPU
program. The handling of a synchronous interrupt
occurs with the actual event that caused the interrupt;
whereas the handling of an asynchronous interrupt may
occur much later in time than the actual event that
caused the interrupt. We discuss the classification,
types (micro, mini, and mainframe computers),
priorities, codes, and handling processes of interrupts.
Classifications of Interrupts
There are two major classifications of interrupts:
internal interrupts and external interrupts.
Internal interrupts Internal interrupts occur as
a result of actions or conditions within the sections of
the computer (CPU, IOCs, or memory). Internal
interrupts tend to indicate the completion or termination
of I/O operations, or the ending of defined time periods;
or they signal some type of error.