DAC Functional Description
The DAC can be divided into three major sections:
the digital section, the analog section, and the power
supply section, as shown in figure 13-7.
DIGITAL SECTION. —The digital section
processes the EF word and the control address word
upon receipt of the EF signal from the computer. If the
control address matches the channel A or B address, the
digital section generates the output data request (ODR)
signal to the computer to start the data word processing.
The computer provides a data word along with the
output acknowledge (OA) signal. The converter then
drops the ODR indicating it has accepted the data. The
data bits are fed to the digital section holding registers
for the applicable channel and subchannels. The output
of the holding registers is fed to the analog section for
conversion to proportional voltages.
ANALOG SECTION. —The primary function of
the analog section is to convert the data words received
from the digital section into proportional analog
voltages. The form of the analog output is dependent
on the mode of operation (TRIG or LINEAR) and,
during the TRIG mode, the type of output selected
(synchro or resolver). The switches for selecting the
converter mode (TRIG/LINEAR) are located on the
base (figure 13-8). The switches for selecting synchro
or resolver operation in the TRIG mode are located on
the DAC front panel (figure 13-6).
Each DAC channel (A or B) is in turn divided into
two subchannels (A1 and A2 or B1 and B2). The data
words accepted by the DAC channel are made up of two
13-bit data words consisting of a polarity bit and a 12-bit
code. In the TRIG mode, the 12-bit code represents the
sine or cosine outputs. In the LINEAR mode, the 12
bits are converted directly to linear voltages. Channel
A1 outputs the sine waveform in the TRIG mode or one
of the linear waveforms in LINEAR mode. Channel A2
outputs the cosine waveform in the TRIG mode and the
second linear waveform in the LINEAR mode. The
polarity bits are used to determine the quadrant in which
the angle lies in the TRIG mode and the polarity of the
linear output in the LINEAR mode.
The actual digital-to-analog conversion is
performed using two resistive ladder networks (one
each for channels A1 and A2). The logic state of the
data and polarity bits controls the operation of analog
switches, which route currents from a ladder network
into a summing network. A reference voltage for the
ladder network is supplied from selected reference
transformers. The selection of the reference
transformers is dependent on the mode of operation and
the state of the applicable polarity bit in the data word.
When the proper reference voltages are selected, the
currents through the ladder network are summed and
applied to the output selection circuit as proportional
voltages.
The channel A1 and channel A2 proportional
voltages represent the sine and cosine voltages for
resolver output. For synchro output, the sine and cosine
voltages are fed to a Scott-tee transformer by the output
selection circuitry. The Scott-tee output consists of the
3-wire, single-speed synchro output.
Figure 13-7.—DAC block diagram.
13-10
